1. Technical Field
The present invention relates generally to peripheral interfaces for computer systems, and more specifically relates to a peripheral interface for communicating data with external devices via dedicated channels.
2. Related Art
Many systems utilize a centralized processor to receive, process, and communicate data to and from remote devices located throughout the system. In systems that perform high-speed functionality, data often must be communicated to and from peripheral devices at very high rates of speed, such that the processor can make quick control decisions.
One example of such a system is a check-sorting system. A typical high-speed check-sorting machine may be required to process 40 documents per second. During such processing, the system may be required to perform numerous interrelated tasks, including analyze checks to determine how they should be routed, take actions when errors occur, capture and process magnetic ink character recognition (MICR) based data, cause information to be printed onto checks, collect and analyze image data, etc. Because the peripheral devices needed to accomplish each of these tasks may reside at different remote locations within the system, a high speed and efficient system for communicating parallel data between a processor and the peripheral devices is critical.
Numerous peripheral interface systems exist that allow data to be communicated between a central processing unit and peripheral devices. However, none provide high-speed, low latency performance necessary for systems, such as the check-sorting machine described above. For instance, U.S. Pat. No. 6,487,628, issued on Nov. 26, 2002, entitled “Peripheral Component Interface with Multiple Data Channels and Reduced Latency over a System Area Network,” which is hereby incorporated by reference, describes a peripheral control interface (PCI) that provides access to a system area network for a plurality of devices connected to the PCI via an I/O bus. In the system, devices are assigned to one of a plurality of channels for the particular transaction. Moreover, the system requires the host computer to interact with the peripheral device to communicate data. Thus, the teachings of this patent consume significant overhead, and would therefore not meet the real-time data communication needs described above.
Accordingly, a need exists for a peripheral interface that can provide high-speed, low latency parallel data communications between a plurality of peripheral devices and a central computer system.